An exemplary prior art method of forming buried bit line DRAM circuitry, and issues associated therewith, is described with reference to FIGS. 1–3. FIGS. 1 and 2 depict circuitry fabrication relative to a memory array, whereas FIG. 3 depicts circuitry fabrication relative to peripheral circuitry which is not within the memory array. A wafer fragment 10 comprises an exemplary bulk monocrystalline substrate 11, for example bulk monocrystalline silicon. Exemplary shallow trench isolation regions 12 are shown formed relative to substrate 11. Within the memory array, exemplary n+ diffusion regions/storage node locations 13 and 15 are formed. An n+ diffusion region/bit line node 14 is also illustrated. A p+ peripheral node 16 is illustrated relative to the peripheral circuitry (FIG. 3). Background doping within the substrate 11 region of FIG. 1 would typically be p−, while that of FIG. 3 would typically be n−.
Exemplary word line/gate line/conductive interconnects 18 are illustrated. Preferred constructions for the same include a gate dielectric layer 20, a conductively doped polysilicon layer 22, a conductive metal silicide layer 24 and an insulative cap 26. Insulative sidewall spacers 28 are also illustrated as comprising a portion of gate constructions 18.
A thin, undoped silicon dioxide layer 30 has been deposited over the substrate. An example material is silicon dioxide deposited by decomposition of tetraethylorthosilicate (TEOS). Another insulating layer 31 has been deposited thereover, with an example being doped silicon dioxide, such as borophosphosilicate glass (BPSG). Such has been planarized, as shown, for example by chemical mechanical polishing (CMP).
A photolithographic masking and etch step is then conducted to form storage node vias 32 and bit line via 34 in a common masking and in one or more common etching steps. A buried contact implant can then be provided, if desired, to within the typically previously formed diffusion regions 13, 14 and 15. Then, n+ polysilicon 36 is provided, typically by in situ doping during deposition, to overfill openings 32 and 34. Such can then be dry etched or CMP'd back to provide the illustrated isolated plugs 36 within openings 32 and 34.
Next, an exemplary illustrated peripheral circuit via 38 is etched within insulative mass 31/30 (FIG. 3). Then, p+ polysilicon 40 is provided within opening 38, typically by in situ doping during deposition. Such polysilicon is then CMP'd or otherwise planarized back to form an isolated plug within peripheral circuitry via 38.
Thereafter, a thin undoped silicon dioxide layer 42 is deposited, preferably by the decomposition of TEOS. Then, photolithographic patterning and oxide etch are conducted to form opening 44 to the bit contact plugging material 36 within bit line via 34. During this step, or more typically at a later step in the process, openings 47 (FIG. 3) are also formed within undoped silicon dioxide layer 42 relative to the peripheral p+ plugging material 40 received within peripheral vias 38.
Metal materials 46 and 48 are blanketly deposited over the substrate. Preferably, material 46 comprises a composite of a physical vapor deposited titanium rich titanium nitride material followed by physical vapor deposition of stoichiometric tungsten nitride. Typically, layer 48 is then deposited by chemical vapor deposition to principally comprise elemental tungsten. An insulative capping layer 51 might also be provided. Metal materials 46 and 48 are subjected to a photolithographic masking and subtractive etching step to form the illustrated buried bit line 52. Nitride spacers 54 can be provided by deposition and anisotropic etch.
Then, another BPSG layer 56 is deposited. Such can be by rapid thermal processing and reflow, or any other process. Nitride can also be etched from the backside of the substrate at this point. The BPSG can then be CMP'd or otherwise planarized back. Another photolithographic masking step and patterning can then be conducted to form the illustrated openings 58 and 60 within insulative materials 56 and 42 to the illustrated material 36 within openings 32, and material 40 within opening 38. Thereafter, conductive plugging material 62 (i.e., conductively doped polysilicon) is provided within openings 58 and 60, and then etched or otherwise planarized back. Subsequent processing is then conducted to form capacitor constructions in electrical contact with material 62 within the array.
Full formation of the contacting plugs to conductive nodes 13, 14, 15 and 16, including the fabrication of the buried bit line, in the above-described process uses five different masking steps, as well as a plethora of deposition steps and dry etch processing. It would be desirable to minimize this complexity and number of steps.
While the invention was motivated in addressing the above issues and improving upon the above-described drawbacks, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded (without interpretative or other limiting reference to the above background art description, remaining portions of the specification, or the drawings), and in accordance with the doctrine of equivalents.